library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;


entity latch4 is
    port (
        i      : in  std_ulogic_vector(3 downto 0);
        o      : out std_ulogic_vector(3 downto 0);
        clk    : in  std_ulogic;
        rst    : in  std_ulogic;
        enable : in  std_ulogic
        );
end latch4;

architecture Behavioral of latch4 is
    component latch
        port (
            i      : in  std_ulogic;
            o      : out std_ulogic;
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
begin
    U0 : latch port map(i(0), o(0), clk, rst, enable);
    U1 : latch port map(i(1), o(1), clk, rst, enable);
    U2 : latch port map(i(2), o(2), clk, rst, enable);
    U3 : latch port map(i(3), o(3), clk, rst, enable);
end Behavioral;
